Simple inverter design in simulink

This example introduces the working principles of a three-phase voltage source inverter and presents a simple technique to generate alternating currents in an open-loop manner, using the imperix ACG SDK on Simulink or PLECS.
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This example introduces the working principles of a three-phase voltage source inverter and presents a simple technique to generate alternating currents in an open-loop manner, using the imperix ACG SDK on Simulink or PLECS.

As such, this simple example can serve as an introduction to the imperix tools, but also as a reference model for performing the first set of tests on new equipment, or simply as a control code for grid-forming inverters or UPS inverters.

The following files contain the implementation of this application in the MATLAB Simulink environment using the ACG SDK. As always, the same model can be used to simulate the behavior of the system in an offline simulation and generate code for real-time execution of the control algorithm on an imperix controller.

This application considers a three-phase two-level voltage source inverter (VSI) connected to a passive RL load, as depicted above. The inverter produces three sinusoidal load currents with configurable amplitude.

As the Carrier-Based PWM modulators of the B-Box RCP controller use a PWM carrier varying between 0 and 1, the modulation signals have to be scaled to fit in the range [0, 1], as depicted below. The duty-cycles are computed as follows:

The duty cycles are generated in an open-loop manner with the expressions of (m_i) and(d_i) presented above. A sinewave generator is implemented using an “angle” block from imperix library, which outputs directly the argument (2pi f t). The Simulink blocks used to compute the duty cycles are shown below.

The present application uses Carrier-based PWM (CB-PWM) modulators to generate the gating signals of the six switches from the computed duty cycles (d_i) and uses a triangular carrier. Each CB-PWM block generates the high- and low-side gating signals for a specific phase leg.

A dead time of 1 µs is added between the ‘on’ states of each pair of complementary signals to avoid destructive shoot-through during the operation of the real inverter. In simulation, the dead time is also modeled and the slight waveform distortion that it brings can be observed in simulation results.

In this application, the phase currents and the DC bus voltage are measured and sent back to the controller’s analog inputs. As no closed-loop control is implemented, these measured quantities are used for monitoring purposes only. In most applications, however, these quantities are required by the control algorithm to compute the duty cycles in a closed-loop manner.

The analog measurements are retrieved by the control code with ADC blocks. The behavior of these blocks in simulation and code generation modes is detailed inADC – Analog data acquisition.

The sampling phase can be configured in the CONFIG block. This application uses a phase of 0.5 and triangular PWM carriers, to ensure that the sampling is always done in the middle of the current ripples. This configuration gives naturally access to an averaged value of each measured currents, without the addition of any filter and its inevitable delay.

About Simple inverter design in simulink

About Simple inverter design in simulink

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